1. Field of the Invention
The present invention relates to a charge-based analog multiplier circuit which generates an output representative of the product of an input signal and a weight voltage. The output product can either be generated as a charge onto an output bus or the amount can be depleted from an output bus to represent a negative result. The circuit of the present invention is particularly useful as a neural cell within a neural network system.
2. Description of the Prior Art
A circuit which produces an output related to the product of an input signal and a weight is a necessary element in many applications. Such circuits are particularly important for massively parallel data processing and cognition performed in artificial neural networks. Many neural networks use massively parallel, digital processing arrays which emulate individual neuron behavior by digital computations in local processing elements (PEs).
In addition to digital techniques, various analog VLSI implementation of neural networks have been known or suggested. Several attributes of these systems include: simplicity of the neural processing elements, natural extensions from actual biological processes to electrical analogies, efficient signal representations and continuous signals.
Various processing elements have been known. For example, U.S. Pat. No. 4,809,193 discloses a matrix of processing elements based on radiant communications among waveguides. Several digital techniques have also been known. See, for example, U.S. Pat. No. 4,591,980 which discloses a matrix of locally-connected digital processing elements.
U.S. Pat. No. 4,796,199 discloses a method of connecting digital processing elements to achieve neural-like computations. These digital techniques are based on current microprocessor techniques and utilize discrete, binary computational elements instead of analog, or continuous signals.
Methods and devices for pattern recognition have also been known. See, for example, U.S. Pat. No. 4,805,225 which discloses a general purpose pattern recognition method and apparatus comprises a hierarchical network of basic recognizers.
Various connectionist systems have also been known. See U.S. Pat. No. 4,858,177 which discloses a minimal connectivity parallel data processing system. U.S. Pat. No. No. 4,813,076 discloses a speech processing apparatus and method. Optical techniques have been disclosed. See, for example, U.S. Pat. No. 4,803,736 which discloses a neural network for machine vision. U.S. Pat. No. 4,849,940 discloses an optical neural net memory, and U.S. Pat. No. 4,862,406 discloses an adaptive associative-processing optical computing architecture.
Self-organizing circuits have been known. See, for example, U.S. Pat. No. 4,774,677 which discloses a circuit using both analog and digital circuitry and which present competition among inputs.
Some charge-based devices have also been known. .For example, a charge-based approach is disclosed in El-Leithy et al., A Basic MOS Neural-Type Junction: A Perspective on Neural-Type Microsystems, Proceedings of the First IEEE International Conference on Neural Networks, San Diego, 1987, Vol. III, pp. 469-477 (1987). The circuit disclosed therein is based on the sensing of incoming impulse signals and an output stage to generate output impulses. The nature of operation of the circuit involves temporal and spatial summation of input impulses. However, a large number of interconnections are necessary with this design which can be very limiting.
There remains a need for a multiplier circuit which produces an output capable of sourcing or sinking an amount proportional to the product of an analog input signal and an analog weight. There remains a further need for such a charge-based analog circuit amenable to use in single-chip, multi-layer neural networks In addition, there remains a need for a circuit the output of which may be multiplexed onto a shared communication bus which connects groups of such circuits.